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Output Control Feature Precedence
The order of applying output control features to the PWM signal is important and significant. Use the following
order for applying the signal features to the PWM output signal.
1. Duty generation
2. Cross-over
3. High-side or low-side disable
4. Emergency dead-time insertion
5. HPPWM correction for wrong programming
6. Gate-drive chopping
7. Polarity
8. Heightened-Precision PWM (HPPWM) edge placement
When HPPWM operation is enabled, the cross-over feature and the gate-drive chopping feature must be
NOTE:
disabled.
Operating Modes
The PWM generator is capable of operating in the following modes:
•
Sync Operation Modes
•
Output Disable and Cross-Over Modes
•
Heightened-Precision Edge Placement
•
Emulation Mode
Sync Operation Modes
The PWMx_SYNC pins can operate as internally generated or externally generated. If its internally generated,
PWMs can drive the signal to synchronize other PWMs and other devices. If externally generated, the PWMs can be
synchronized externally.
External (Triggered) PWM Sync Generation
By setting the PWM_CTL.EXTSYNC bit, the PWM is set up in a mode to expect an external PWM_SYNC signal on
the PWM_SYNC_IN pin through the TRU. The trigger source can be any TRU1 trigger master. Multiple PWM
units can be precisely synchronized by selecting the same trigger master as the sources for each PWM sync trigger
slave. Examples of useful trigger masters include:
• A PWM_SYNC GPIO master. This option allows synchronizing the PWMs to an off-chip timing source. (The
PWM_CTL.EXTSYNC bit must be programmed to 1 to enable the GPIO input.) The PWM_SYNC GPIO pads
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Functional Description
19–25
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