Analog Devices ADSP-SC58 Series Hardware Reference Manual page 634

ADSP-SC58x PORT Register Descriptions
Table 14-23: PORT_POL Register Fields (Continued)
Bit No.
(Access)
14 PX14
(R/W)
13 PX13
(R/W)
12 PX12
(R/W)
11 PX11
(R/W)
10 PX10
(R/W)
9 PX9
(R/W)
8 PX8
(R/W)
14–62
Bit Name
Port x Bit 14 Polarity Invert.
The PORT_POL.PX14 bit enables polarity inversion.
Port x Bit 13 Polarity Invert.
The PORT_POL.PX13 bit enables polarity inversion.
Port x Bit 12 Polarity Invert.
The PORT_POL.PX12 bit enables polarity inversion.
Port x Bit 11 Polarity Invert.
The PORT_POL.PX11 bit enables polarity inversion.
Port x Bit 10 Polarity Invert.
The PORT_POL.PX10 bit enables polarity inversion.
Port x Bit 9 Polarity Invert.
The PORT_POL.PX9 bit enables polarity inversion.
Port x Bit 8 Polarity Invert.
The PORT_POL.PX8 bit enables polarity inversion.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 No Invert. GPIO is active high or rising edge sensitive.
1 Invert. GPIO is active low or falling edge sensitive.
0 No Invert. GPIO is active high or rising edge sensitive.
1 Invert. GPIO is active low or falling edge sensitive.
0 No Invert. GPIO is active high or rising edge sensitive.
1 Invert. GPIO is active low or falling edge sensitive.
0 No Invert. GPIO is active high or rising edge sensitive.
1 Invert. GPIO is active low or falling edge sensitive.
0 No Invert. GPIO is active high or rising edge sensitive.
1 Invert. GPIO is active low or falling edge sensitive.
0 No Invert. GPIO is active high or rising edge sensitive.
1 Invert. GPIO is active low or falling edge sensitive.
0 No Invert. GPIO is active high or rising edge sensitive.
1 Invert. GPIO is active low or falling edge sensitive.