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6. Program the
EPPI_VDLY
7. Program the
EPPI_VCNT
8. If setting up the EPPI for transmit, the data enable (DEN) pin behaves according to the enabling of the blank-
ing generation and the data length setting (DLEN). See
mit Mode
for more details.
9. Enable DMA.
10. Enable the EPPI.
11. To program the EPPI in internal clock mode, follow the procedure above with the EPPI_CTL.ICLKGEN bit
=0. After enabling the EPPI, add a delay of 200 SCLK1_0 cycles (worst case) to ensure the EPPI FIFO be-
comes full. Then switch to internal clock mode by setting the EPPI_CTL.ICLKGEN bit =1.
Data moves in or out of memory. A frame sync frames the data for every line and frame.
Configuring Transfers in GP 3 FS Mode
GP 3 FS mode is useful for video applications that use three synchronization signals for hardware: HSYNC,
VSYNC, and FIELD. The HSYNC connects to EPPI_FS1, VSYNC connects to EPPI_FS2, and FIELD con-
nects to EPPI_FS3.
1. Configure the EPPI to operate in GP 3 FS mode by setting the EPPI_CTL.XFRTYPE bit =b#11 and the
EPPI_CTL.FSCFG bit =b#11. An external device can provide the frame syncs or the EPPI can source the
frame syncs.
2. Configure the windowing registers according to steps in GP 2 FS mode.
3. Enable DMA.
4. Enable the EPPI.
5. To program the EPPI in internal clock mode, follow the procedure above with the EPPI_CTL.ICLKGEN bit
=0. After enabling the EPPI, add a delay of 200 SCLK1_0 cycles (worst case) to ensure the EPPI FIFO be-
comes full. Then switch to internal clock mode by setting the EPPI_CTL.ICLKGEN bit =1.
Data moves in or out of memory. A frame sync frames the data for every line and frame. Operation and result are
similar to operation in GP 2 FS mode but the EPPI also uses the EPPI_FS3 signal.
Configuring the EPPI to Use the Windowing Feature
Windowing is a useful feature for applications where the region of interest is smaller than the active video stream
(for example, sensor calibration, auto-focusing, and others). It can result in significant DMA bandwidth reduction.
The EPPI supports windowing for GP input modes.
1. Program the
EPPI_FRAME
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register to contain the number of lines to wait after the start of frame is detected.
register to contain the number of lines to receive or transmit.
register with the number of lines the frame contains.
Data Enable in General-Purpose 2 Frame Sync Trans-
EPPI Programming Model
18–33
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