Analog Devices ADSP-SC58 Series Hardware Reference Manual page 4

A5 Configurations ...................................................................................................................................... 2-7
Clock Generation Unit (CGU)
CGU Features ................................................................................................................................................ 3-1
CGU Functional Description......................................................................................................................... 3-1
ADSP-SC58x CGU Register List................................................................................................................ 3-2
ADSP-SC58x CGU Interrupt List ............................................................................................................. 3-2
ADSP-SC58x CGU Trigger List ................................................................................................................. 3-3
CGU Definitions........................................................................................................................................ 3-3
CGU PLL Block Diagram .......................................................................................................................... 3-4
CGU Operating Modes ................................................................................................................................. 3-6
CGU Power-up Sequence .............................................................................................................................. 3-6
CGU Event Control ...................................................................................................................................... 3-6
Oscillator Watchdog .................................................................................................................................. 3-7
CGU Programming Model ............................................................................................................................ 3-8
Configuring CGU Modes ........................................................................................................................... 3-8
Changing Clock Frequencies ................................................................................................................... 3-9
Changing the PLL Clock Frequency ........................................................................................................ 3-9
Changing the CCLKn or SYSCLK Frequency Without Modifying the PLLCLK Frequency ................. 3-10
Changing the OCLK Frequency ............................................................................................................ 3-11
Aligning All Clocks ............................................................................................................................... 3-11
Shutting Off CCLKn From Another Master.......................................................................................... 3-12
Valid Clock Multiplier Settings ............................................................................................................ 3-12
PLL Bypass and PLL Disable ................................................................................................................ 3-13
ADSP-SC5xx Specific Information........................................................................................................ 3-13
ADSP-SC58x CGU Register Descriptions .................................................................................................. 3-13
Core Clock Buffer Disable Register ......................................................................................................... 3-15
Core Clock Buffer Status Register ............................................................................................................ 3-16
CLKOUT Select Register ........................................................................................................................ 3-17
Control Register ...................................................................................................................................... 3-19
Clocks Divisor Register ........................................................................................................................... 3-21
iv ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference