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Master Trigger Register
The TRU master trigger register (TRU_MTR) permits trigger generation through software by writing a trigger mas-
ter ID value to one of the four fields in the
=1) and the TRU_GCTL.LOCK bit is set, the
debug to trigger a TRU output
MTR1 (R/W)
Master Trigger Register 1
MTR3 (R/W)
Master Trigger Register 3
Figure 8-4: TRU_MTR Register Diagram
Table 8-8: TRU_MTR Register Fields
Bit No.
(Access)
31:24
MTR3
(R/W)
23:16
MTR2
(R/W)
15:8
MTR1
(R/W)
7:0
MTR0
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
TRU_MTR
TRU_MTR
15
14
13
12
11
10
9
0
0
0
0
0
0
0
31
30
29
28
27
26
25
0
0
0
0
0
0
0
Bit Name
Master Trigger Register 3.
The TRU_MTR.MTR3 bit field is the trigger master ID value for master 3.
Master Trigger Register 2.
The TRU_MTR.MTR2 bit field is the trigger master ID value for master 2.
Master Trigger Register 1.
The TRU_MTR.MTR1 bit field is the trigger master ID value for master 1.
Master Trigger Register 0.
The TRU_MTR.MTR0 bit field is the trigger master ID value for master 0.
register. If the global lock is enabled (SPU_CTL.GLCK bit
register is read only. Note this register is primarily used for
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
24
23
22
21
20
19
18
17
0
0
0
0
0
0
0
0
Description/Enumeration
0 No master specified
1-139 Range of valid masters
0 No master specified
1-139 Range of valid masters
0 No master specified
1-139 Range of valid masters
0 No master specified
1-139 Range of valid masters
ADSP-SC58x TRU Register Descriptions
0
0
MTR0 (R/W)
Master Trigger Register 0
16
0
MTR2 (R/W)
Master Trigger Register 2
8–19
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