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Boot ROM and Booting the Processor
SRAM Requirements ................................................................................................................................... 53–1
Preboot Operations...................................................................................................................................... 53–3
Start-up Sequence..................................................................................................................................... 53–3
Core Reset Sequencing .......................................................................................................................... 53–3
Core 0 Start-up ..................................................................................................................................... 53–5
Core 1 Start-up ..................................................................................................................................... 53–6
Core 2 Start-up ..................................................................................................................................... 53–7
Idle On Entry ........................................................................................................................................... 53–8
Fault Configuration .................................................................................................................................. 53–8
SPU Configuration................................................................................................................................... 53–9
SMPU Configuration ............................................................................................................................... 53–9
Secure Debug Key Processing ................................................................................................................. 53–10
CGU Configuration ............................................................................................................................... 53–11
Releasing All Cores From Reset .............................................................................................................. 53–13
L1/L2 Memory Initialization.................................................................................................................. 53–13
Default Application Entry Points............................................................................................................ 53–14
Memory Faults Configuration ................................................................................................................ 53–14
NO-BOOT Processing ........................................................................................................................... 53–15
SYS_RESOUTb Processing .................................................................................................................... 53–15
DMC Configuration .............................................................................................................................. 53–16
Bypassing the Boot Process..................................................................................................................... 53–17
Boot Mode Disable................................................................................................................................. 53–17
Boot Command Customization.............................................................................................................. 53–17
Boot Mode Specific SPU Configuration ................................................................................................. 53–18
Executing the Boot Mode ....................................................................................................................... 53–18
Boot Modes .............................................................................................................................................. 53–19
No-Boot Mode ....................................................................................................................................... 53–20
SPI Master Boot Mode ........................................................................................................................... 53–20
SPI Slave Boot Mode ............................................................................................................................. 53–27
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ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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