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Figure 11-12: Asynchronous FIFO Write Bus Cycles
SMC Programming Model
The following general guidelines are used for configuring and enabling the SMC interface. Failure to follow these
guidelines can lead to erroneous behavior.
• In asynchronous page mode, always program SMC_B0CTL.RDYEN to 0.
• Enable the ARDY abort counter (the SMC_B0CTL.RDYABTEN bit =1) whenever the SMC_ARDY signal is
enabled (the SMC_B0CTL.RDYEN is set to 1). This step ensures that the interface does not hang due to erro-
neous SMC_ARDY signal behavior or erroneous sampling of the SMC_ARDY signal.
• Do not program read access time (SMC_B0TIM.RAT), write access time (SMC_B0TIM.WAT), read setup
time (SMC_B0TIM.RST), and write setup time (SMC_B0TIM.WST) to 0.
• Never program page mode wait-states (SMC_B0ETIM.PGWS) to 0 or 1.
• Program the page size bits (SMC_B0CTL.PGSZ) to match the configurations of the flash device connected to
the SMC interface.
• Select the SMC_B0CTL.RDYPOL bit to be the complement of the WAIT polarity that is configured in the
flash device.
• In asynchronous SRAM and asynchronous flash modes with SMC_ARDY enabled, and where
SMC_B0TIM.RHT, SMC_B0TIM.WHT, SMC_B0TIM.RAT, and SMC_B0TIM.WAT are the read and write
hold and access times and SMC_B0ETIM.IT and SMC_B0ETIM.TT are the idle and transition times, en-
sure that the following conditions are true:
• SMC_B0TIM.RHT + SMC_B0ETIM.IT + SMC_B0ETIM.TT≥ 2
• SMC_B0TIM.WHT + SMC_B0ETIM.IT + SMC_B0ETIM.TT≥ 2
• SMC_B0TIM.RAT≥ 5
• SMC_B0TIM.WAT≥ 5
ADSP-SC58x SMC Register Descriptions
Static Memory Controller (SMC) contains the following registers.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
CLKOUT
AMS(n)/WE
DATA/DIN
WD0
Write
Write
Setup
Access
1 Cycle
3 Cycles
1 Cycle
WD1
Write
Trans.
Hold
TURN
2 Cycles
SMC Programming Model
11–17
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