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SMPU Functional Description
Table 13-1: SMPU Instances (Continued)
Module
DMC0
DMC1
All the SMPU instances can be configured up to eight regions.
• Up to eight outstanding read or write transactions supported on SMPU instances for
Core_L2_RAM_Boot_ROM0, DMC0 and DMC1.
• Up to four outstanding read or write transactions supported on the SMPU instances for
DMA_L2_RAM_Boot_ROM0, Core_L2_ROM1_Boot_ROM1, DMA_L2_ROM1_Boot_ROM1,
Core_L2_ROM2_Boot_ROM2, DMA_L2_ROM2_Boot_ROM2, SMC, and PCIe.
• Exclusive access enabled by hardware for the SMPU instances of Core_L2_RAM_Boot_ROM0, DMC 0,
DMC1, and SMC. Up to four exclusive-access-capable masters can be supported.
SMPU Functional Description
The following sections provide details on the function of the SMPU module. If the region security settings allow
transactions to go through, the ID in the ID-based region protection settings can still filter the transactions.
For the memory that an SMPU protects, programs can configure region-based settings with the
registers. (There can be multiple SMPUs in a system.) The
tion for memory regions.
If the target address does not reside in any configured memory region, the transaction permission resorts back to the
global configuration setting.
Protection Units
Each SMPU provides two protection units, A and B for ID-based matching in the region-based memory protection.
This feature provides a degree of flexibility for the user to match against multiple IDs.
Instruction Fetches
When the core executes instructions from memory, this operation is also considered a memory transaction. If the
SMPU is configured to protect a memory region from read accesses that contain instructions, the core cannot fetch
and execute these instructions.
Using Cache
When the processor uses both cache and the SMPU, there are a few issues to be aware of. If the SMPU is configured
to protect a memory region from write accesses, instruction fetches from a core are still possible since instructions
are not updated and replaced during run time.
13–2
SMPU Instance
9
10
SMPU_RCTL[n]
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SMPU_RCTL[n]
registers define the ID-based protec-
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