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Architectural Concepts
port is driving data from the shift register to the pins. The LP_STAT.LPBS bit is also set when receiver has held
off transmission by driving LP_ACK low.
When the 2-deep FIFO and the output shift-register overflow, any further write to the link port buffer
NOTE:
overwrites the input stage of the FIFO.
NOTE:
The core can also read the transmit FIFO through the data
If the transmitter is disabled while performing writes to the transmit FIFO, a FIFO full condition is sig-
NOTE:
naled after two writes.
The transmit buffer registers have shadow registers. Using these shadow registers, both stages of the 2-deep FIFO
can be read without updating the status registers. The
the FIFO. The
LP_TXOUT_SHDW
FIFO path figure.
Figure 15-7: Transmit FIFO path
When a link port is configured as receiver, data transfers to the core or DMA from the full 4-deep receive FIFO. An
internal packing register packs data to 32 bits. Four reads can occur from the receive buffer by the core or DMA
before it signals an empty condition. The link port uses the LP_STAT.FFST bits to reflect the status of the 4-deep
read buffer FIFO. The core can access this FIFO through the
NOTE:
When receive FIFO overflows (LP_STAT.ROVF bit=1), any further data from the transmitter is lost.
Only the data retained in the receive FIFO can be retrieved further.
The receiver drives the LP_ACK output signal low, after the first byte of data for the next-to-last empty slot (in the
4-deep FIFO) is received. This functionality prevents data loss due to the transmitter starting transmission of the
next word before the LP_ACK signal reaches the transmitter. (The timing is due to the larger delay in synchroniza-
tion.) This functionality guarantees that even after allowing for the extra synchronization cycle in the transmitter
and receiver, there is no overflow in the receive FIFO. The LACK Generation Based on Receive FIFO Status figure
15–8
register corresponds to the output stage of the FIFO as shown in the Transmit
SHIFT REGISTER
FIFO OUTPUT
STAGE
FIFO
STATUS
FIFO INPUT
STAGE
WRITE ACCESS VIA
DATA REGISTER
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
LP_TX
register.
LP_TXIN_SHDW
register corresponds to the input stage of
SHADOW REGISTER FOR
OUTPUT STAGE
SHADOW REGISTER FOR
INPUT STAGE
LP_RX
register.
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