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Contents
Power and Clock Management (DPM/RCU/CGU/CDU) ............................................................................ 1-2
System Interrupts and Triggers (SEC/TRU) .................................................................................................. 1-3
System Memory (L2CTL/DMC/SMC/OTPC/SMPU) ................................................................................. 1-4
Direct Memory Access (DMA/MDMA/EMDMA/CRC)............................................................................... 1-7
Peripherals ..................................................................................................................................................... 1-9
General-Purpose I/O (GPIO) Peripherals................................................................................................... 1-9
DAI/SRU Peripherals ............................................................................................................................... 1-14
Dedicated Pin Peripherals......................................................................................................................... 1-15
System Accelerators (FFT/FIR/IIR/HAE/SINC) ......................................................................................... 1-17
Security and Protection (SPU/PKTE/PKIC/PKA/TRNG).......................................................................... 1-19
Safety (WDOG/TMU/VMU) ..................................................................................................................... 1-20
Analog Subsystem (HADC) ......................................................................................................................... 1-20
System Debug (SCB/SWU/DBG/TAPC/CSPFT/STM) ............................................................................. 1-20
Cortex A5 Features ........................................................................................................................................ 2-1
Functional Description .................................................................................................................................. 2-2
A5 Block Diagram ...................................................................................................................................... 2-2
Control Co-Processor (CP15)..................................................................................................................... 2-2
L1 Cache .................................................................................................................................................... 2-3
Prefetch Unit (PFU) ................................................................................................................................... 2-3
Memory-Management Unit (MMU) .......................................................................................................... 2-3
L2 Cache .................................................................................................................................................... 2-4
Floating-Point Unit (FPU) ......................................................................................................................... 2-5
NeON ........................................................................................................................................................ 2-6
Generic Interrupt Controller (GIC)............................................................................................................ 2-7
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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