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• Overall system control and configuration
• MMU configuration and management
• Cache configuration and management
• System performance monitoring
All system architecture functions are controlled by reading or writing a general purpose processor register (Rt) from
or to a set of registers (CRn) located within co-processor 15. The Op1, Op2, and CRm fields of the instruction can
also be used to select registers or operations.
• MRC p15, Op1, Rt, CRn, CRm, Op2; read a CP15 register into an ARM register
• MCR p15, Op1, Rt, CRn, CRm, Op2; write a CP15 register from an ARM register
L1 Cache
The Cortex-A5 processor has separate instruction and data caches that run at ARM Core clock speed. The caches
have the following features:
• L1-Data Cache size 32 KB
• L1-Instruction Cache size 32 KB
• Each cache can be disabled independently, using the system control coprocessor
• Cache replacement policy is pseudo random
• Data cache is 4-way set-associative
• Instruction cache is 2-way set-associative
• The cache line length is eight words.
• On a cache miss, critical word first filling of the cache is performed.
Prefetch Unit (PFU)
The PFU implements a two-level prediction mechanism, comprising the following:
• A 256 entry branch pattern history table
• A four-entry BTAC
• A four-entry return stack
Memory-Management Unit (MMU)
The ARM MMU is responsible for translating addresses of code and data from the virtual view of memory to the
physical addresses in the real system. The translation is carried out by the MMU hardware and is transparent to the
application. In addition, the MMU controls such things as memory access permissions, memory ordering and cache
policies for each region of memory.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Functional Description
2–3
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