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Figure 1-39: SINC System Diagram
Security and Protection (SPU/PKTE/PKIC/PKA/TRNG)
The following modules provide system safety and security.
System Protection Unit (SPU)
In a system with multiple system MMR masters, configurations of peripherals can be changed unintentionally lead-
ing to bad data or even system malfunctions. The peripherals are shared resources in the system. The
tion Unit (SPU)
restricts access to certain MMRs, similar to the functionality of a semaphore.
The SPU also protects peripherals based on security settings. It is part of the overall security infrastructure of the
processor.
Security Packet Engine (PKTE)
The PKTE is a security packet engine designed to off-load the host processor to improve the speed of applications
requiring cryptographic processing. The packet engine contains a set of modules for encryption and decryption,
hashing, and pseudo-random number generation.
Public Key Accelerator (PKA)
The
Public Key Accelerator (PKA)
key cryptography algorithms. The PKA also contains hardware logic to automatically zero out the PKA RAM buffer
to clear out any information that is considered sensitive or secure.
Public Key Interrupt Controller (PKIC)
The
Public Key Interrupt Controller (PKIC)
ber Generator. The host processor configures the PKIC to generate interrupts when certain operations are complete
or interrupts are caused by errors.
True Random Number Generator (TRNG)
The
True Random Number Generator (TRNG)
ing keys, Initialization Vectors (IVs), and other random number requirements. Other non-cryptographic purposes
include statistical sampling, retry timers for communications protocols and noise generation.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SINC
SINC0_CLK0
PB_01 Pin
SINC0_D0
PA_14 Pin
SINC0_D1
PA_15 Pin
SINC0_D2
PB_00 Pin
SINC0_D3
PB_04 Pin
Clocked by SCLK0_0
helps offload computationally-intensive operations commonly found in public
is a common interrupt controller shared with the True Random Num-
SINC Status Interrupt (SINC0_STAT) to SEC/GIC
SINC Pair Overload Triggers (SINC0_Px_OVLD) to TRU Slaves
SINC Data Move Triggers (SINC0_DATAx) to TRU Slaves
System MMR Write-Protection (WP60) from SPU
Enable Secure Peripheral (SECUREP60) from SPU
engine provides a true, non-deterministic, noise source for generat-
Security and Protection (SPU/PKTE/PKIC/PKA/TRNG)
System Protec-
1–19
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