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ADSP-SC58x SMPU Register Descriptions
Region n Control Secure Accesses Register
The
SMPU_SECURERCTL[n]
WSECDIS (R/W)
Secure Write Transaction Disable
WNSEN (R/W)
Non-secure Write Transaction Enable
Figure 13-17: SMPU_SECURERCTL[n] Register Diagram
Table 13-21: SMPU_SECURERCTL[n] Register Fields
Bit No.
(Access)
3
WSECDIS
(R/W)
2
WNSEN
(R/W)
1
RSECDIS
(R/W)
0
RNSEN
(R/W)
13–34
register contains bits that configure read/write security for a specific region.
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
Bit Name
Secure Write Transaction Disable.
The SMPU_SECURERCTL[n].WSECDIS bit disables secure write transactions for
the memory region.
Non-secure Write Transaction Enable.
This SMPU_SECURERCTL[n].WNSEN bit enables non-secure write transactions
for the memory region.
Secure Read Transaction Disable.
The SMPU_SECURERCTL[n].RSECDIS bit disables secure read transactions for
the memory region.
Non-secure Read Transaction Enable.
The SMPU_SECURERCTL[n].RNSEN bit enables non-secure read transactions for
the memory region.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
Description/Enumeration
0 Enable secure write transactions to this region
1 Disable secure write transactions to this region
0 Disable non-secure write transactions to this region
1 Enable non-secure write transactions to this region
0 Enable secure read transactions to this region
1 Disable secure read transactions to this region
0 Disable non-secure read transactions to this region
1 Enable non-secure read transactions to this region
RNSEN (R/W)
Non-secure Read Transaction Enable
RSECDIS (R/W)
Secure Read Transaction Disable
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