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SPI Programming Concepts
Configuring DMA Master Mode
The SPI interface supports a write DMA channel and a read DMA channel. It can use these functions individually
or in a lock-step manner in duplex mode (SPI_TXCTL.TTI= SPI_RXCTL.RTI=1).
1. Write to the appropriate DMA registers to enable the SPI DMA channel and to configure the necessary work
units, access direction, word count, and so on.
2. Write to the
SPI_SLVSEL
3. Write to the SPI_CLK and
tem by specifying the appropriate word length, transfer format, baud rate, and so forth.
4. Write to
SPI_RXCTL
transmit mode.
5. Finally, write to the SPI_RXCTL.REN bit to enable the receive channel, or write to SPI_TXCTL.TEN to
enable the transmit channel.
6. If the SPI_RXCTL.RTI bit is enabled, a receive transfer is initiated upon enabling SPI_CTL.EN bit. If the
receive word counter is enabled (SPI_RXCTL.RWCEN), then the
transfer to initiate.
ADDITIONAL INFORMATION: If enabling both receive and transmit DMA channels, but not enabling
SPI_TXCTL.TTI, write to the
ters. In this way, a transmit underrun can be prevented for the first transfer. Subsequent transfers are initiated as
the SPI reads data from the receive shift register and writes to the SPI receive FIFO. The SPI then requests a
write from DMA to memory. Upon a DMA grant, the DMA engine reads a word from the SPI receive FIFO
and writes to memory. New requests continue to be initiated as long as the receive FIFO does not fill up, when
SPI_RWC
does not become zero while SPI_RXCTL.RWCEN=1.
7. If SPI_TXCTL.TTI is enabled, the SPI controller requests DMA reads from memory as long as there is space
for more data in the transmit pipe. Upon a DMA grant, the DMA engine reads a word from memory and
writes to the transmit FIFO. As long as transmit data is available in the FIFO, and the
non-zero when SPI_TXCTL.TWCEN=1, the SPI continues to initiate transfers until disabled.
8. If both the SPI_TXCTL.TTI and SPI_RXCTL.RTI bits are enabled, the SPI controller requests a DMA
read from memory. However, there must be space for more data in the transmit pipe and the number of words
written into the SPI must be less than
engine reads a word from memory and writes to the transmit FIFO.
ADDITIONAL INFORMATION: As the SPI writes data from the transmit FIFO into the transmit shift regis-
ter, it initiates a transfer on the SPI link. Data received from the transfer is moved from the SPI receive shift
register to the receive FIFO. The SPI controller requests a write from DMA to memory. Upon a DMA grant,
the DMA engine reads a word from the receive FIFO and writes to memory. Transfer continues to be initiated
as long as both receives and transmits can accommodate new data.
16–32
register, setting one or more of the SPI flag select bits.
registers, enabling the device as a master and configuring the SPI sys-
SPI_CTL
to configure SPI master receive mode, or write to
SPI_RXCTL
SPI_TWC
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SPI_RWC
register after writing the
if SPI_TXCTL.TWCEN=1. Upon a DMA grant, the DMA
SPI_TXCTL
to configure SPI master
register must be non-zero for a
SPI_CTL
and
SPI_TXCTL
SPI_TWC
regis-
register is
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