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EPPI Operating Modes
General-Purpose EPPI Modes
The general-purpose (GP) EPPI modes accommodate a wide variety of data capture and transmission applications.
Each EPPI has three bidirectional frame sync pins. The EPPI internally generates frame syncs, or an external device
communicating with the EPPI generates them.
GP modes differ based on the number of frame syncs used and the EPPI supports GP 0 FS—GP 3 FS modes.
All the GP modes, except 0 FS mode, support horizontal windowing. GP modes with 2 and 3 frame syncs also
support vertical windowing.
For GP transmit modes with internal clock or frame syncs, the EPPI starts generating the clock or frame syncs only
when the EPPI FIFO is full for the first time. For GP 0 FS transmit mode, the EPPI only starts transmitting when
the EPPI FIFO is full for the first time.
General-Purpose 0 Frame Sync Mode
This mode is useful for applications where periodic frame syncs are not used to frame the data.
After the initial trigger, the EPPI receives or transmits data samples on every clock cycle. However, if the
EPPI_CTL.SKIPEN bit is set for receive mode, the EPPI receives only alternate data samples.
The EPPI_LINE, EPPI_FRAME, EPPI_HCNT, EPPI_HDLY, EPPI_VCNT, and
not valid for GP 0 FS mode. Therefore, windowing is not possible in this mode. Also, line and frame track errors are
not applicable in this mode.
GP 0 FS receive mode is further divided into two submodes; internal trigger (EPPI_CTL.FLDSEL bit =0) and
external trigger (EPPI_CTL.FLDSEL bit =1). The submodes are based on how the processor initiates data trans-
mission or reception. GP 0 FS transmit mode is always internally triggered. DMA handles all subsequent data ma-
nipulation.
• Frame synchronization in GP 0 FS external trigger mode. When the EPPI is programmed in external trigger
mode, it does not generate the EPPI_FS1 signal and the external device must provide a trigger. The EPPI
starts receiving the data as soon as an EPPI_FS1 signal assertion is detected. After that, the DMA handles all
subsequent data manipulation and any activity on EPPI_FS1 is ignored.
• Frame synchronization in GP 0 FS internal trigger mode. When the EPPI is programmed in internal trigger
mode, it starts receiving or transmitting data as soon as the EPPI clock is enabled and synchronized. There can
be up to four PPI clock cycles of latency before valid data is received or transmitted.
General-Purpose 1 Frame Sync Mode
This mode is useful for interfacing the EPPI with analog-to-digital converters (ADCs), digital-to-analog converters
(DACs), and other general-purpose devices. This mode works for both transmit and receive.
The EPPI_FRAME, EPPI_VDLY, and
track errors and vertical windowing are not available.
18–20
EPPI_VCNT
registers have no effect in GP 1 FS mode. As a result, frame
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
registers are
EPPI_VDLY
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