Analog Devices ADSP-SC58 Series Hardware Reference Manual page 797

UART Operating Modes
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Multi-Drop Bus Mode
UART Mode
The UART mode follows an asynchronous serial communication protocol with these options:
• 1 start bit
• 5–8 data bits
• Address bit (available in MDB mode only)
• None, even, odd or sticky parity
• 1, 1½, or 2 stop bits (1½ stop bits valid only in 5-bit word length)
The UART_CTL register controls the format of received and transmitted character frames. Data is always transmit-
ted and received with the least significant bit (LSB) first.
The Bit Stream on a UART TX Pin Transmitting an "S" Character (0x53) figure shows a typical physical bit stream
measured on a UART_TX pin.
Figure 17-5: Bit Stream on a UART TX Pin Transmitting an "S" Character (0x53)
IrDA SIR Mode
The UART also supports serial data communication by way of infrared signals, according to the recommendations
of the Infrared Data Association (IrDA). The physical layer known as IrDA SIR (9.6/115.2 Kbps rate) is based on
return-to-zero-inverted (RZI) modulation. The UART does not support pulse position modulation.
Using the 16x data rate clock, RZI modulation is achieved by inverting and modulating the non-return-to-zero
(NRZ) code normally transmitted by the UART. On the receive side, the UART uses a 16x clock to determine an
IrDA pulse sample window, from which it recovers the RZI modulated NRZ code.
NOTE: The UART_CLK.EDBO bit is not valid in IrDA mode. Clear (=0) this bit in this mode.
Multi-Drop Bus Mode
The UART uses a protocol for point-to-point connections as well as in networks where the EIA-485 standard is
representative of UART-based bus systems. The EIA-232 standard defines point-to-point connections. In such net-
works, node addressing is important.
17–10
DATA BITS
D0 D1 D2
START BIT LSB
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
D3 D4 D5 D6 D7
PARITY BIT (OPTIONAL, ODD OR EVEN)
STOP BIT(S)