Table of Contents
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SMI Read Operation........................................................................................................................ 31–68
EMAC Management Counters (MMC) .............................................................................................. 31–68
MMC Receive Interrupt Register .................................................................................................... 31–70
MMC Transmit Interrupt Register .................................................................................................. 31–70
MMC Receive Checksum Offload Interrupt Register ...................................................................... 31–70
EMAC Precision Time Protocol (PTP) Engine ................................................................................... 31–70
IEEE1588 and the PTP Engine ....................................................................................................... 31–70
Block Diagram ................................................................................................................................ 31–74
PTP Module Clock .......................................................................................................................... 31–75
Time Stamp Module ........................................................................................................................ 31–77
System Time .................................................................................................................................... 31–84
Target Time Trigger (Alarm) ............................................................................................................ 31–87
Pulse-Per-Second (PPS).................................................................................................................... 31–87
PTP Interrupts................................................................................................................................. 31–90
Audio Video Data Transmission .......................................................................................................... 31–90
Transmit Path Functions .................................................................................................................. 31–91
Receive Path Functions .................................................................................................................... 31–92
DMA Arbiter ................................................................................................................................... 31–93
Slot Number Function ..................................................................................................................... 31–94
Interrupts......................................................................................................................................... 31–94
Credit-Based Shaper Algorithm Functions ....................................................................................... 31–94
Energy-Efficient Ethernet .................................................................................................................... 31–96
Transmit Path Functions .................................................................................................................. 31–96
Receive Path Functions .................................................................................................................... 31–97
LPI Timers....................................................................................................................................... 31–99
EMAC Event Control ................................................................................................................................ 31–99
EMAC Interrupt Signals....................................................................................................................... 31–100
PHYINT Interrupt Signal ................................................................................................................ 31–101
EMAC Programming Model.................................................................................................................... 31–102
EMAC Programming Steps .................................................................................................................. 31–102
DMA Initialization............................................................................................................................ 31–102
EMAC CORE Initialization .............................................................................................................. 31–103
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ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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