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ADSP-SC58x EPPI Register Descriptions
FS2 Period Register / EPPI Active Lines Per Field Register
The
EPPI_FS2_PALPF
transmit mode.
In GP 2 or 3 FS modes,
period required for EPPI_FS2 based on the EPPI_CLK clock.
In GP transmit mode with the EPPI_CTL.BLANKGEN bit set, this register contains the number of lines of active
video per field.
Note that a value of 0 for the EPPI_FS2_PALPF.F1ACT or EPPI_FS2_PALPF.F2ACT bits is illegal. If ei-
ther is programmed as 0, the EPPI regards the 0 value fields as containing 1.
Also, note that for progressive video, the EPPI_FS2_PALPF.F2ACT bit is ignored.
Figure 18-23: EPPI_FS2_PALPF Register Diagram
Table 18-57: EPPI_FS2_PALPF Register Fields
Bit No.
(Access)
31:16
F2ACT
(R/W)
15:0
F1ACT
(R/W)
18–70
register content varies depending on whether the EPPI is in GP2/3 FS modes or in GP
is used for the generation of frame sync 2. This register contains the
EPPI_FS2_PALPF
15
14
13
0
0
0
F1ACT (R/W)
Field 1 Active
31
30
29
0
0
0
F2ACT (R/W)
Field 2 Active
Bit Name
Field 2 Active.
The EPPI_FS2_PALPF.F2ACT bit field contains the number of lines of active da-
ta in field 2.
Field 1 Active.
The EPPI_FS2_PALPF.F1ACT bit field contains the number of lines of active da-
ta in field 1.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
28
27
26
25
24
23
22
21
0
0
0
0
0
0
0
0
Description/Enumeration
4
3
2
1
0
0
0
0
0
0
20
19
18
17
16
0
0
0
0
0
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