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Global Status Register
The SEC global status register (SEC_GSTAT) contains global status bits for the SEC.
LWERR (R/W1C)
Lock Write Error
ADRERR (R/W1C)
Address Error
Figure 7-26: SEC_GSTAT Register Diagram
Table 7-25: SEC_GSTAT Register Fields
Bit No.
(Access)
31
LWERR
(R/W1C)
30
ADRERR
(R/W1C)
23:16
SID
(R/NW)
11:8
SCI
(R/NW)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
0
0
0
0
0
SCI (R)
SCI ID for SCI Error
ERRC (R)
Error Cause
31
30
29
28
27
26
0
0
0
0
0
Bit Name
Lock Write Error.
The SEC_GSTAT.LWERR bit indicates (when set) there was an attempted write to
an SEC register while the SEC_GCTL.LOCK bit was set and while the global lock bit
was enabled (SPU_CTL.GLCK bit =1). This status bit is sticky; write-1-to-clear it.
Address Error.
The SEC_GSTAT.ADRERR bit indicates that the SEC generated and address error.
This status bit is sticky; write-1-to-clear it.
Source ID for SSI Error.
The SEC_GSTAT.SID bits indicate the source ID that generated the last SSI error
conveyed in the SEC_GSTAT.ERRC field.
SCI ID for SCI Error.
The SEC_GSTAT.SCI bits indicate the number for the specific SCI that generated
the last SCI error conveyed in the SEC_GSTAT.ERRC field.
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
0 No Error
1 Error Occurred
0 No Error
1 Error Occurred
ADSP-SC58x SEC Register Descriptions
2
1
0
0
0
0
ERR (R/W1C)
Error
17
16
0
0
0
SID (R)
Source ID for SSI Error
7–51
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