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iATU Region Control 3 Register ......................................................................................................... 29–211
iATU Region Control 3 Register ......................................................................................................... 29–212
IATU Lower Base Inbound Address Register ....................................................................................... 29–213
IATU Lower Base Outbound Address Register .................................................................................... 29–214
IATU Inbound Limit Address Register ................................................................................................ 29–215
IATU Outbound Limit Address Register ............................................................................................. 29–216
IATU Lower Target Address Inbound Register .................................................................................... 29–217
IATU Lower Target Address Outbound Register ................................................................................. 29–218
IATU Upper Base Address Inbound Register ....................................................................................... 29–219
IATU Upper Base Address Outbound Register .................................................................................... 29–220
iATU Upper Target Address Inbound Register .................................................................................... 29–221
iATU Upper Target Address Outbound Register ................................................................................. 29–222
IATU View Port Register ..................................................................................................................... 29–223
Lane Skew Register .............................................................................................................................. 29–224
Link Capabilities 2 Register ................................................................................................................. 29–226
Link Capabilities Register .................................................................................................................... 29–227
Link Control 2 and Status 2 Register ................................................................................................... 29–232
Link Control and Status Register ......................................................................................................... 29–236
DBI Read-Only Write Enable Register ................................................................................................ 29–239
MSI Capability ID, Next Pointer and Control Register ....................................................................... 29–240
MSI Capability Offset Register ............................................................................................................ 29–242
MSI Capability Offset Register ............................................................................................................ 29–243
MSI Capability Offset Register ............................................................................................................ 29–244
MSI Controller Lower Address Register .............................................................................................. 29–245
MSI Controller Upper Address Register .............................................................................................. 29–246
MSI Controller General-Purpose IO Register ...................................................................................... 29–247
MSI Controller Interrupt 0 Enable Register ........................................................................................ 29–248
MSI Controller Interrupt 1 Enable Register ........................................................................................ 29–249
MSI Controller Interrupt 2 Enable Register ........................................................................................ 29–250
MSI Controller Interrupt 3 Enable Register ........................................................................................ 29–251
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ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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