Analog Devices ADSP-SC58 Series Hardware Reference Manual page 8

Core/SEC Handshaking Requirements to Ensure Proper Interrupt Handling ....................................... 7–20
Configuring a System Source as a Fault ................................................................................................. 7–20
Configuring the WDOG Expiry Event to Issue a System Reset ............................................................. 7–21
SEC Programming Restrictions ................................................................................................................ 7–21
ADSP-SC58x SEC Register Descriptions .................................................................................................... 7–22
SCI Active Register n ............................................................................................................................... 7–24
SCI Control Register n ............................................................................................................................ 7–25
SCI Group Mask Register n ..................................................................................................................... 7–27
SCI Priority Level Register n ................................................................................................................... 7–29
SCI Priority Mask Register n ................................................................................................................... 7–31
Core Pending Register n .......................................................................................................................... 7–32
SCI Source ID Register n ........................................................................................................................ 7–33
SCI Status Register n ............................................................................................................................... 7–34
Global End Register ................................................................................................................................. 7–36
Fault COP Period Register ...................................................................................................................... 7–37
Fault COP Period Current Register ......................................................................................................... 7–38
Fault Control Register ............................................................................................................................. 7–39
Fault Delay Register ................................................................................................................................ 7–42
Fault Delay Current Register ................................................................................................................... 7–43
Fault End Register ................................................................................................................................... 7–44
Fault Source ID Register .......................................................................................................................... 7–45
Fault System Reset Delay Register ........................................................................................................... 7–46
Fault System Reset Delay Current Register .............................................................................................. 7–47
Fault Status Register ................................................................................................................................ 7–48
Global Control Register ........................................................................................................................... 7–50
Global Status Register ............................................................................................................................. 7–51
Global Raise Register ............................................................................................................................... 7–53
Source Control Register n ........................................................................................................................ 7–54
Source Status Register n ........................................................................................................................... 7–57
GIC Overview ............................................................................................................................................. 7–58
viii ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference