Analog Devices ADSP-SC58 Series Hardware Reference Manual page 299

ADSP-SC58x SEC Register Descriptions
Source Control Register n
The SEC source control register (SEC_SCTL[n]) contains control bits to configure the SEC event sources. This
register controls the configuration of the corresponding SEC event source.
PRIO (R/W)
Priority Level Select
ERREN (R/W)
Error Enable
ES (R/W)
Edge Select
LOCK (R/W)
Lock
CTG (R/W)
Core Target Select
Figure 7-28: SEC_SCTL[n] Register Diagram
Table 7-27: SEC_SCTL[n] Register Fields
Bit No.
(Access)
31 LOCK
(R/W)
27:24 CTG
(R/W)
7–54
15 14 13 12 11 10 9
0 0 0 0 0 0 0
31 30 29 28 27 26 25
0 0 0 0 0 0 0
Bit Name
Lock.
If the global lock is enabled (SPU_CTL.GLCK bit =1) and the
SEC_SCTL[n].LOCK bit is enabled, the
Core Target Select.
The SEC_SCTL[n].CTG bits selects the specific SEC core interface to which the in-
terrupt is mapped. Each system interrupt is mapped uniquely to one specific SEC core
interface and (as a result) to a specific core.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
24 23 22 21 20 19 18 17
0 0 0 0 0 0 0 0
Description/Enumeration
0 Unlock
1 Lock
0
0
IEN (R/W)
Interrupt Enable
FEN (R/W)
Fault Enable
SEN (R/W)
Source (signal) Enable
16
0
GRP (R/W)
Group Select
SEC_SCTL[n] register is read only.