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SMPU Functional Description
Table 13-3: System Master IDs (Continued)
Master Name
FIR_CH1
IIR_CH0
IIR_CH1
EMDMA0_CH0
EMDMA0_CH1
EMDMA1_CH0
EMDMA1_CH1
STD_BW_MDMA_SRC_CH
STD_BW_MDMA_DST_CH
PCIE_M
ENH_BW_MDMA_SRC_CH
ENH_BW_MDMA_DST_CH
FFT_CH0
FFT_CH1
SH0_DPORT
SH0_IPORT
SH1_DPORT
SH1_IPORT
PL310_M0 = L2 cache Master Port 0
PL310_M0 = L2 cache Master Port 1
DBG
ETR
Memory Region
Memory regions can start at address 0x00000000 or at any address that is a multiple of its size. The Supported
Memory Region Size and Alignment table shows the memory region sizes that the processor supports and the align-
ment of the memory region. (X values are do-not-care).
SMPU0 and SMPU2 support a maximum of four regions. SMPU1 supports a maximum of eight regions.
Table 13-4: Supported Memory Region Size and Alignment
Size
13–8
SCB Input Switch
5
6
6
7
7
7
7
8
8
8
9
9
9
9
10
10
10
10
10
10
3
3
SMPU_RCTLn.SIZE
0b00000
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Master ID SCB Input
ID
7
13'b0101000000111
6
13'b0110000000110
7
13'b0110000000111
0
13'b0111000000000
1
13'b0111000000001
2
13'b0111000000010
3
13'b0111000000011
0
13'b10000000x0000
1
13'b10000000x0001
2
13'b1000xxxxx0010
0
13'b10010000x0000
1
13'b10010000x0001
2
13'b10010000x0010
3
13'b10010000x0011
0
13'b1010000000000
1
13'b1010000000001
2
13'b1010000000010
3
13'b1010000000011
5
13'b1010xxxxx0101
4
13'b1010xxxxx0100
3
13'b0011000000011
4
13'b0011000000100
Address
0xXXXXX000
Possible Values for N
-
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