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SMPU Status Register
The
register provides the state of the SMPU and indicates various errors. All bits in this register are
SMPU_STAT
write 1 to clear.
BEOVR (R/W1C)
Bus Error Overrun
BERR (R/W1C)
Bus Error
LWERR (R/W1C)
Lock Write Error
Figure 13-18: SMPU_STAT Register Diagram
Table 13-22: SMPU_STAT Register Fields
Bit No.
(Access)
17
LWERR
(R/W1C)
16
ADRERR
(R/W1C)
3
BEOVR
(R/W1C)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
Bit Name
Lock Write Error.
The SMPU_STAT.LWERR bit is set when SMPU_CTL.LOCK bit =1, the global lock
signal is asserted from the SPU and a read or write attempt was made to the
SMPU_CTL
Address Error.
The SMPU_STAT.ADRERR bit is set when the SMPU MMR is accessed as an un-
aligned address, or when a read-only MMR is written to.
Bus Error Overrun.
The SMPU_STAT.BEOVR bit indicates that another bus error had occurred. Any
new information about the most recent violation which caused the bus error is not
captured.
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
MMR.
0 No Lock Write Error
1 Lock Write Error
0 No Address Error
1 Address Error
0 No Bus Error overrun
1 Bus Error overrun has occurred
ADSP-SC58x SMPU Register Descriptions
2
1
0
0
0
0
IRQ (R/W1C)
Interrupt Request
IOVR (R/W1C)
Interrupt Overrun
17
16
0
0
0
ADRERR (R/W1C)
Address Error
13–35
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