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Static Memory Controller (SMC)
SMC Features .............................................................................................................................................. 11–1
SMC Definitions ......................................................................................................................................... 11–1
SMC Functional Description ....................................................................................................................... 11–3
ADSP-SC58x SMC Register List.............................................................................................................. 11–4
SMC Architectural Concepts .................................................................................................................... 11–4
Avoiding Bus Contention ...................................................................................................................... 11–5
ARDY Input Control ............................................................................................................................ 11–6
SMC Operating Modes................................................................................................................................ 11–6
Asynchronous Flash Mode........................................................................................................................ 11–7
Asynchronous Page Mode......................................................................................................................... 11–7
SMC Event Control..................................................................................................................................... 11–7
SMC Programmable Timing Characteristics................................................................................................ 11–7
Asynchronous SRAM Reads and Writes.................................................................................................... 11–7
Asynchronous SRAM Reads with IDLE Transition Cycles Inserted.......................................................... 11–9
High-Speed Asynchronous SRAM Read Burst.......................................................................................... 11–9
High-Speed Asynchronous SRAM Writes ............................................................................................... 11–10
Asynchronous SRAM Reads with ARDY ................................................................................................ 11–11
Asynchronous Flash Reads...................................................................................................................... 11–12
Asynchronous Flash Writes ..................................................................................................................... 11–14
Asynchronous Flash Page Mode Reads.................................................................................................... 11–15
Asynchronous FIFO Reads and Writes .................................................................................................. 11–15
SMC Programming Model ........................................................................................................................ 11–17
ADSP-SC58x SMC Register Descriptions ................................................................................................ 11–17
Bank 0 Control Register ........................................................................................................................ 11–19
Bank 0 Extended Timing Register ......................................................................................................... 11–22
Bank 0 Timing Register ......................................................................................................................... 11–24
Bank 1 Control Register ........................................................................................................................ 11–26
Bank 1 Extended Timing Register ......................................................................................................... 11–29
Bank 1 Timing Register ......................................................................................................................... 11–31
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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