Changing Clock Frequencies; Changing The Pll Clock Frequency - Analog Devices ADSP-SC58 Series Hardware Reference Manual

*pREG_CGU0_PLLCTL |= BITM_CGU_PLLCTL_PLLBPCL; // come out of bypass and enter
Full ON
while( (pADI_CGU0 ->STAT & 0xF) != 0x5 ) { } // poll
// now clocks are running with hardware default divisors.
// now program can change frequencies If desired the program can put the PLL
again into bypass.

Changing Clock Frequencies

Applications change clock frequencies in two ways. The first way is modifying the PLL multiplication value by writ-
ing to the register and the second is modifying the clock dividers by writing to the
CGU_CTL
Both actions have different implications even if the frequencies of the final clock are the same. Write accesses to
change the CGU_CTL.DF or CGU_CTL.MSEL bit fields while the PLL is locking set the
CGU_STAT.WDFMSERR error bit. The CGU_STAT.WDIVERR error bit is set when one of following accesses is
attempted while the PLL is locked, but still aligning the clocks:
• A write access to the
• A write access to the
CGU_DIV.S0SEL, CGU_DIV.S1SEL, or CGU_DIV.DSEL bits
Read-after-write accesses to these registers return the new value, even if the frequency of the clock change is still in-
progress.
Modifying the PLL multiplier requires the PLL to relock. Once the PLL locks, the CGU synchronizes the clocks.
Changes to the CGU_CTL.DF or CGU_CTL.MSEL bit field result in bypassing the PLL. By setting the
CGU_CTL.WFI bit, programs force the PLL to wait for all the cores to return to their idle or reset states before the
frequency changes. If necessary, clear the CGU_DIV.UPDT bit to avoid multiple clock alignment sequences. If the
CGU_DIV register is not updated, the CGU uses the current values to determine the frequencies of the clock. It is
the programs responsibility to guarantee that the new CGU_CTL.DF or CGU_CTL.MSEL and
nations are legal.

Changing the PLL Clock Frequency

To change the phase-locked loop clock (PLLCLK) frequency, write new values to the CGU_CTL.MSEL field or
CGU_CTL.DF field. Any time the PLL relocks, all core and system clocks are aligned.
1. Read CGU_STAT
a. The CGU_STAT.PLLEN bit =1 (PLL enabled)
b. The CGU_STAT.PLOCK bit =1 (PLL is not locking)
c. The CGU_STAT.CLKSALGN bit =0 (clocks aligned)
2. Write the desired values to the clock divisor select fields of the
bit =0.
3. Write the desired values to the CGU_CTL.DF and CGU_CTL.MSEL fields.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register to trigger an alignment sequence
CGU_DIV
register to change the CGU_DIV.CSEL, CGU_DIV.SYSSEL,
CGU_DIV
register and verify that:
CGU_DIV register with the CGU_DIV.UPDT
Configuring CGU Modes
register.
CGU_DIV
CGU_DIV combi-
3–9