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ADSP-SC58x SMC Register Descriptions
Bank 2 Timing Register
The
register configures bank 2 read and write access, setup, and hold timing for this bank. Note that
SMC_B2TIM
read and write timing configurations are independent and may differ.
WAT (R/W)
Write Access Time
WHT (R/W)
Write Hold Time
RAT (R/W)
Read Access Time
RHT (R/W)
Read Hold Time
Figure 11-21: SMC_B2TIM Register Diagram
Table 11-11: SMC_B2TIM Register Fields
Bit No.
(Access)
29:24
RAT
(R/W)
22:20
RHT
(R/W)
11–38
15
14
13
12
11
10
0
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
0
Bit Name
Read Access Time.
The SMC_B2TIM.RAT bits select the access time (in SCLK0_0 cycles) that the SMC
asserts the SMC_ARE pin for a read access. The access time is from 1 to 63 SCLK0_0
cycles.
Read Hold Time.
The SMC_B2TIM.RHT bits select the hold time (in SCLK0_0 cycles) that the SMC
waits after de-asserting the SMC_ARE pin before asserting the SMC_AOE pin for the
next access. The hold time is from 0 to 7 SCLK0_0 cycles.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
9
8
7
6
5
4
3
2
0
1
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
1
0
0
0
0
0
0
Description/Enumeration
0 Not supported
1 1 SCLK0_0 clock cycle
63 63 SCLK0_0 clock cycles
0 0 SCLK0_0 clock cycles
1 1 SCLK0_0 clock cycle
7 7 SCLK0_0 clock cycles
1
0
0
1
WST (R/W)
Write Setup Time
17
16
0
1
RST (R/W)
Read Setup Time
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