Analog Devices ADSP-SC58 Series Hardware Reference Manual page 616

ADSP-SC58x PORT Register Descriptions
Table 14-16: PORT_FER_CLR Register Fields (Continued)
Bit No.
(Access)
6 PX6
(R/W1C)
5 PX5
(R/W1C)
4 PX4
(R/W1C)
3 PX3
(R/W1C)
2 PX2
(R/W1C)
1 PX1
(R/W1C)
0 PX0
(R/W1C)
14–44
Bit Name
Port x Bit 6 Mode Clear.
The PORT_FER_CLR.PX6 bit enables GPIO mode.
Port x Bit 5 Mode Clear.
The PORT_FER_CLR.PX5 bit enables GPIO mode.
Port x Bit 4 Mode Clear.
The PORT_FER_CLR.PX4 bit enables GPIO mode.
Port x Bit 3 Mode Clear.
The PORT_FER_CLR.PX3 bit enables GPIO mode.
Port x Bit 2 Mode Clear.
The PORT_FER_CLR.PX2 bit enables GPIO mode.
Port x Bit 1 Mode Clear.
The PORT_FER_CLR.PX1 bit enables GPIO mode.
Port x Bit 0 Mode Clear.
The PORT_FER_CLR.PX0 bit enables GPIO mode.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 No Effect
1 Set Bit for GPIO Mode
0 No Effect
1 Set Bit for GPIO Mode
0 No Effect
1 Set Bit for GPIO Mode
0 No Effect
1 Set Bit for GPIO Mode
0 No Effect
1 Set Bit for GPIO Mode
0 No Effect
1 Set Bit for GPIO Mode
0 No Effect
1 Set Bit for GPIO Mode