Analog Devices ADSP-SC58 Series Hardware Reference Manual page 385

Sharc+ processor
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Table 9-6: L2CTL_CTL Register Fields (Continued)
Bit No.
(Access)
15
ECCMAP7
(R/W)
14
ECCMAP6
(R/W)
13
ECCMAP5
(R/W)
12
ECCMAP4
(R/W)
11
ECCMAP3
(R/W)
10
ECCMAP2
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
ECC Map Bank 7.
The L2CTL_CTL.ECCMAP7 bit selects whether L2 bank 7 addresses ECC RAM or
data RAM.
ECC Map Bank 6.
The L2CTL_CTL.ECCMAP6 bit selects whether L2 bank 6 addresses ECC RAM or
data RAM.
ECC Map Bank 5.
The L2CTL_CTL.ECCMAP5 bit selects whether L2 bank 5 addresses ECC RAM or
data RAM.
ECC Map Bank 4.
The L2CTL_CTL.ECCMAP4 bit selects whether L2 bank 4 addresses ECC RAM or
data RAM.
ECC Map Bank 3.
The L2CTL_CTL.ECCMAP3 bit selects whether L2 bank 3 addresses ECC RAM or
data RAM.
ECC Map Bank 2.
The L2CTL_CTL.ECCMAP2 bit selects whether L2 bank 2 addresses ECC RAM or
data RAM.
ADSP-SC58x L2CTL Register Descriptions
Description/Enumeration
0 Data RAM
1 ECC RAM
0 Data RAM
1 ECC RAM
0 Data RAM
1 ECC RAM
0 Data RAM
1 ECC RAM
0 Data RAM
1 ECC RAM
0 Data RAM
1 ECC RAM
9–13

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