Table of Contents
Advertisement
SCI Priority Level Register n
The SEC SCI priority level register (SEC_CPLVL[n]) contains selections for priority levels and a register lock.
This register is used to divide the total number of priority levels into sub-levels. The sub-level priority resolution
provides the tie breaker for simultaneously pending interrupts assigned to the same level.
Figure 7-9: SEC_CPLVL[n] Register Diagram
Table 7-8: SEC_CPLVL[n] Register Fields
Bit No.
(Access)
31
LOCK
(R/W)
2:0
PLVL
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
0
0
0
PLVL (R/W)
Priority Levels
31
30
29
0
0
0
LOCK (R/W)
Lock
Bit Name
Lock.
If the global lock is enabled (SPU_CTL.GLCK bit =1) and the
SEC_CPLVL[n].LOCK bit is enabled, the
Priority Levels.
The SEC_CPLVL[n].PLVL field serves to divide the total number of interrupt pri-
ority levels into sub-levels. The sub-level priority resolution provides the tie breaker for
simultaneously pending interrupts assigned to the same interrupt level. The sub-level
priority value specifies the number of MSBs (minus 1) designated to interrupt levels,
while the remaining LSBs are designated for sub-level specification.
For example, if the SEC_CPLVL[n].PLVL field is set to two, the result is four pri-
ority levels are specified, because only the two MSBs are used for preemption evalua-
tion. The remaining bits of the priority setting are used for sub-level prioritization.
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
28
27
26
25
24
23
22
21
0
0
0
0
0
0
0
0
Description/Enumeration
0 Unlock
1 Lock
0 1 MSBs (2 priority levels)
1 2 MSBs (4 priority levels)
2 3 MSBs (8 priority levels)
3 4 MSBs (16 priority levels)
4 5 MSBs (32 priority levels)
5 6 MSBs (64 priority levels)
ADSP-SC58x SEC Register Descriptions
4
3
2
1
0
0
0
1
1
1
20
19
18
17
16
0
0
0
0
0
SEC_CPLVL[n]
register is read only.
7–29
Advertisement
Table of Contents
