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Architectural Concepts
5. The receiver accepts the remaining word even if LP_ACK is deasserted. The transmitter does not send the fol-
lowing word.
6. Transmission of data for next word is held until LP_ACK is asserted.
The transmitter samples the LP_ACK signal. If the signal is high, the transmitter gives out the falling edges of
LP_CLK for data sampling. The LP_ACK signal is first sampled at the rising edge of CDU0_CLKO4. One more
CDU0_CLKO4 stage synchronizes the signal further. This synchronized signal is given to the subsequent logic. The
LP_CLK falling edge is aligned with CDU0_CLKO4 falling edge in a 1:1 clock ratio mode and with the SCLK
rising edge for the rest of the clock ratios. The following figures explain how the synchronization is maintained be-
tween the LP_ACK and LP_CLK signals.
In the following figure, synchronizing time is guaranteed to be 1.5 CDU0_CLKO4 cycles.
SCLK
LP_CLK driven
low if LP_ACK
is sampled by
the previous
SCLK rise edge
Figure 15-4: LP_ACK Synchronization for SCLK:LP_CLK=1:1
In the following figure, synchronizing time is guaranteed to be 2 CDU0_CLKO4 cycles.
15–6
LP_ACK may
deassert after
BYTE 0
LP_ACK driven
by receiver
LP_ACK synchronized
at rising edge
SCLK (2-stage)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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