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ADSP-SC58x SEC Register Descriptions
Fault System Reset Delay Register
The SEC fault system reset delay register (SEC_FSRDLY) contains the number (SEC_FSRDLY.COUNT field) of
(SEC) clock periods for the delay from a fault becoming active to system reset request assertion, if enabled.
COUNT[31:16] (R/W)
Fault System Reset Delay
Figure 7-22: SEC_FSRDLY Register Diagram
Table 7-21: SEC_FSRDLY Register Fields
Bit No.
(Access)
31:0
COUNT
(R/W)
7–46
15
0
COUNT[15:0] (R/W)
Fault System Reset Delay
31
0
Bit Name
Fault System Reset Delay.
The SEC_FSRDLY.COUNT bit field is the number of (SEC) clock periods for the
delay from a fault becoming active to system reset request assertion.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
14
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
30
29
28
27
26
25
24
23
0
0
0
0
0
0
0
0
Description/Enumeration
6
5
4
3
2
1
0
0
0
0
0
0
0
0
22
21
20
19
18
17
16
0
0
0
0
0
0
0
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