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Timer Units
• The register value of the timer must be equal to the
• The
PWM_TM0
are not allowed.
PWM Timer Period (PWM_TM) Registers
The 16-bit read/write PWM period registers
cy. The fundamental timing unit of the PWM controller is t
ns for a 100-MHz system clock (SCLK0_0) frequency, f
tively the number of t
SCLK0_0
required timer register value as a function of the desired PWM switching frequency (f
PWM_TM = f
/2 × f
SCLK0_0
Therefore, the PWM switching period (T
T
= 2 × PWM_TM × t
s
For example, for an f
SCLK0_0
ms), the correct value to load into the timer register is:
6
PWM_TM = 100 × 10
The largest value that can be written to the 16-bit timer register is 0xFFFF = 65,535. For an f
this value corresponds to a minimum PWM switching frequency of:
6
f
= 100 × 10
PWM(min)
Timer register values of 0 and 1 are not defined. Do not use these values when the PWM outputs or PWM
NOTE:
is enabled.
Timer Unit Operation
The PWM timers are up-down counters, and they operate on the peripheral clock with a period of t
of the PWM timer is divided into two halves. In the first half, the timer roughly counts down from PWM_TMx/2
to –PWM_TMx/2. During this half, the PWM_STAT.TMR0PHASE through PWM_STAT.TMR4PHASE bits are
held at 0. In the second half of the period, the timer roughly counts up from –PWM_TMx/2 to PWM_TMx/2.
The PWM_STAT.TMR0PHASE through PWM_STAT.TMR4PHASE bits indicates a 1 during this half.
The actual partition of the periods varies slightly between odd and even values of the half-period, in the
PWM_TM[n] registers.
If a timer register value is odd, for example 11, then that timer loads +5 at the beginning of the period. The timer
counts down from +5 to –5 in the first half, reloads –5 at the midpoint and counts up from –5 to +5 in the second
half. The reload values at the period and mid-period boundaries are the same as the previous count. The timer
counts 2 × 11 half-periods = 22 total counts in the entire period as shown in the Operation of Timer for Odd Value
of PWM_TM figure.
19–8
value must be an integer multiple of each register of the timer. Non-integer multiples
(PWM_TM0
clock increments in one half of a PWM period. The following equation describes the
PWM
) is:
s
SCLK0_0
of 100 MHz and a desired PWM switching frequency (f
3
÷ 2 × 10 × 10
= 5000
÷ 2 x 65535 = 762 Hz
PWM_TM0
through PWM_TM4) control the PWM switching frequen-
. Therefore, the time increment (t
SCLK0_0
. The value written to the register of a timer is effec-
SCLK0_0
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register value.
):
PWM
) of 10 kHz (T
PWM
SCLK0_0
CK
) is 10
SCLK0_0
= 100
s
of 100 MHz,
. The period
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