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2. Install interrupt handlers for DMA and for transfer status (service request interrupt).
3. Configure the link port to transmit by setting the
by setting the LP_CTL.TRQMSK bit.
4. Program the link port clock divider by writing a value to the
5. If using DMA stop mode or auto buffer mode, program the appropriate DMA registers.
ADDITIONAL INFORMATION: An example configuration is: DMA_ADDRSTART, DMA_XCNT,
DMA_XMOD, and
DMA_CFG
generation and memory read).
6. Wait for the link port receiver (connected externally) to be enabled. The application can wait for the transmit
service request interrupt to assert.
7. Clear the transmit service request interrupt status by writing 1 to the LP_STAT.LTRQ bit.
8. Enable DMA by setting the DMA_CFG.EN bit.
9. Enable the link port by setting the LP_CTL.EN bit.
10. Wait for DMA to assert a transfer completion interrupt.
11. Clear the DMA interrupt source by writing 1 to the DMA_STAT.IRQDONE bit.
Setting Up a DMA Receive Operation
This section describes the typical steps for using the link ports in DMA receive mode.
1. Enable the link port pins in GPIO port mux using the appropriate
2. Install interrupt handlers for DMA and for transfer status (service request interrupt).
3. Configure the link port for reception (clear the LP_CTL.TRAN bit) and enable the receive request interrupt
mask by setting the LP_CTL.RRQMSK bit.
4. If using DMA stop mode or auto buffer mode, program the DMA registers.
ADDITIONAL INFORMATION: An example configuration is: DMA_ADDRSTART, DMA_XCNT,
DMA_XMOD, and
DMA_CFG
generation and memory write).
5. If using DMA array mode or list mode, create DMA configuration data structures filled with components.
ADDITIONAL INFORMATION: An example configuration is: DMA_ADDRSTART, DMA_XCNT,
DMA_XMOD, and
DMA_CFG
generation, memory write and fetch =4/5) and
DMA configuration register (Array/List, DMA_CFG.PSIZE =1, DMA_CFG.MSIZE =4, Memory Write and
Fetch =4/5) and program the
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
LP_CTL
registers (Stop/Auto, DMA_CFG.PSIZE =1, DMA_CFG.MSIZE =4, interrupt
registers (Stop/Auto, DMA_CFG.PSIZE=1, DMA_CFG.MSIZE=4, interrupt
registers (Array/List, DMA_CFG.PSIZE =1, DMA_CFG.MSIZE =4, interrupt
DMA_DSCPTR_NXT
DMA_DSCPTR_NXT
register (if list mode).
bit and enable the transmit request interrupt mask
register.
LP_DIV
PORT_FER
and
register (if list mode). Further, program
LP Programming Model
PORT_MUX
registers.
15–15
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