Table of Contents
Advertisement
ADSP-SC58x EPPI Register Descriptions
Vertical Delay Count Register
The
register contains the number of lines to wait after the start of a new frame before starting to read/
EPPI_VDLY
transmit data.
Figure 18-32: EPPI_VDLY Register Diagram
Table 18-66: EPPI_VDLY Register Fields
Bit No.
(Access)
15:0
VALUE
(R/W)
18–82
15
14
13
0
0
0
VALUE (R/W)
Vertical Delay Count
31
30
29
0
0
0
Bit Name
Vertical Delay Count.
The EPPI_VDLY.VALUE holds the number of lines to wait after the start of a new
frame before starting to read/transmit data.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
28
27
26
25
24
23
22
21
0
0
0
0
0
0
0
0
Description/Enumeration
4
3
2
1
0
0
0
0
0
0
20
19
18
17
16
0
0
0
0
0
Advertisement
Table of Contents
