Analog Devices ADSP-SC58 Series Hardware Reference Manual page 43

Current Buffer Descriptor Address Register ........................................................................................... 26–55
Bus Mode Register ................................................................................................................................. 26–56
Byte Count Register .............................................................................................................................. 26–58
Card Detect Register ............................................................................................................................. 26–59
Card Threshold Control Register ........................................................................................................... 26–60
Clock Divider Register .......................................................................................................................... 26–61
Clock Enable Register ............................................................................................................................ 26–62
Command Register ................................................................................................................................ 26–63
Command Argument Register ............................................................................................................... 26–69
Control Register .................................................................................................................................... 26–70
Card Type Register ................................................................................................................................ 26–73
Descriptor List Base Address Register .................................................................................................... 26–74
Debounce Count Register ...................................................................................................................... 26–75
Current Host Descriptor Address Register ............................................................................................. 26–76
Enable Phase Shift Register ................................................................................................................... 26–77
FIFO Threshold Watermark Register .................................................................................................... 26–78
Internal DMA Interrupt Enable Register ............................................................................................... 26–79
Internal DMA Status Register ............................................................................................................... 26–81
Interrupt Mask Register ......................................................................................................................... 26–84
Raw Interrupt Status Register ................................................................................................................ 26–88
Masked Interrupt Status Register ........................................................................................................... 26–92
Poll Demand Register ............................................................................................................................ 26–96
Response Register 0 ............................................................................................................................... 26–97
Response Register 1 ............................................................................................................................... 26–98
Response Register 2 ............................................................................................................................... 26–99
Response Register 3 ............................................................................................................................. 26–100
Status Register ..................................................................................................................................... 26–101
Transferred Host to BIU-FIFO Byte Count Register ........................................................................... 26–104
Transferred CIU Card Byte Count Register ......................................................................................... 26–105
Timeout Register ................................................................................................................................. 26–106
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference xliii