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Table 10-2: ADSP-SC58x DMC Register List
Name
DMC_CAL_PADCTL0
DMC_CAL_PADCTL2
DMC_PHY_CTL0
DMC_PHY_CTL1
DMC_PHY_CTL2
DMC_PHY_CTL3
DMC_PHY_CTL4
Protocol Controller
The DDR SDRAM protocol controller translates memory access requests from the SCB (system crossbar) interface
to JEDEC protocol-specific transactions used by DDR SDRAM devices.
The protocol controller ensures that the various timing parameters are met before reading and writing the SDRAM.
The controller also performs the SDRAM initialization sequence as mandated by the standard. The protocol con-
troller can:
• Issue reads and writes
• Precharge a row in a bank
• Activate a row in a bank
• Put the SDRAM devices in self-refresh and power-down modes
The protocol controller takes mode register writes from the MMR interface and translates them into mode register
writes to SDRAM. Writing into the mode register is restricted through a mask register.
Efficiency Controller
The efficiency controller controls the ordering of transfers buffered in the read and write command buffers. It at-
tempts to order transfers to optimize the available memory bandwidth. The DMC uses a number of schemes, descri-
bed in the following sections, to increase the throughput.
Page-Based Scheduling
The DMC parses each write and read transaction that it buffered and gets the information of the row (page) and
bank address. The protocol controller maintains the information about the pages that are opened in each bank. The
efficiency controller uses the information about the opened pages while scheduling the buffered transactions. The
transactions to the opened pages are given higher priority than the other outstanding transactions.
Same Master Transaction Scheduling
The DMC also stores the ID of each transaction that it buffered. In most of the cases, the transactions related to a
master result in page hits from the locality of reference rule. The efficiency controller uses the ID information of the
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description
Calibration PAD Control 0 Register
Calibration PAD Control 2 Register
PHY Control 0 Register
PHY Control 1 Register
PHY Control 2 Register
PHY Control 3 Register
PHY Control 4 Register
DMC Functional Description
10–5
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