Analog Devices ADSP-SC58 Series Hardware Reference Manual page 835

ADSP-SC58x UART Register Descriptions
Table 17-19: UART_STAT Register Fields (Continued)
Bit No.
(Access)
1 OE
(R/W1C)
0 DR
(R/NW)
17–48
Bit Name
Overrun Error.
The UART_STAT.OE bit indicates that further data is received while the internal re-
ceive buffer was full. This bit is set when sampling the stop bit of the sixth data word.
To avoid overruns, read the
runs are very unlikely to happen ever. After an overrun occurs, the
receive FIFO are protected from being overwritten by new data until the
UART_STAT.OE bit is cleared by software. The content of the
lost as soon as the overrun occurs. The UART_STAT.OE bit is sticky and can be
cleared by W1C operations.
Data Ready.
The UART_STAT.DR bit indicates that data is available in the receiver and can be
read from the
the first valid stop bit. The bit is cleared by hardware when the
read.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
UART_RBR register in time. In DMA receive mode, over-
0 No overrun
1 Overrun error
UART_RBR register. The bit is set by hardware when the receiver detects
0 No new data
1 New data in RBR
UART_RBR and
UART_RSR register is
UART_RBR register is