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FS2 Width Register / EPPI Lines Of Vertical Blanking Register
The
EPPI_FS2_WLVB
transmit mode.
In GP 2 or 3 FS modes, the
contains the width required for EPPI_FS2 based on the EPPI_CLK clock.
In GP transmit mode with the EPPI_CTL.BLANKGEN bit set, this register contains the number or lines of verti-
cal blanking.
Note that for progressive video, the EPPI_FS2_WLVB.F2VBBD and EPPI_FS2_WLVB.F2VBAD bits are ig-
nored.
F1VBAD (R/W)
Field 1 Vertical Blanking After Data
F2VBAD (R/W)
Field 2 Vertical Blanking After Data
Figure 18-24: EPPI_FS2_WLVB Register Diagram
Table 18-58: EPPI_FS2_WLVB Register Fields
Bit No.
(Access)
31:24
F2VBAD
(R/W)
23:16
F2VBBD
(R/W)
15:8
F1VBAD
(R/W)
7:0
F1VBBD
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register content varies depending on whether the EPPI is in GP2/3 FS modes or in GP
EPPI_FS2_WLVB
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
Bit Name
Field 2 Vertical Blanking After Data.
The EPPI_FS2_WLVB.F2VBAD bit field contains the number of lines of vertical
blanking after field 2.
Field 2 Vertical Blanking Before Data.
The EPPI_FS2_WLVB.F2VBBD bit field contains the number of lines of vertical
blanking before field 2.
Field 1 Vertical Blanking After Data.
The EPPI_FS2_WLVB.F1VBAD bit field contains the number of lines of vertical
blanking after field 1.
Field 1 Vertical Blanking Before Data.
The EPPI_FS2_WLVB.F1VBBD bit field contains the number of lines of vertical
blanking before field 1.
register is used for the generation of frame sync 2. The register
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x EPPI Register Descriptions
F1VBBD (R/W)
Field 1 Vertical Blanking Before Data
F2VBBD (R/W)
Field 2 Vertical Blanking Before Data
18–71
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