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ADSP-SC58x MLB Register Descriptions ................................................................................................ 28–27
Peripheral Channel Mask 0 Register ...................................................................................................... 28–29
Peripheral Channel Mask 1 Register ...................................................................................................... 28–30
Peripheral Channel Status 0 Register ..................................................................................................... 28–31
Peripheral Channel Status 1 Register ..................................................................................................... 28–32
Bus Control Register ............................................................................................................................. 28–33
MediaLB Control 0 Register .................................................................................................................. 28–35
Control 1 Register ................................................................................................................................. 28–37
MLB Global Control Register ............................................................................................................... 28–38
HBI Channel Busy 0 Register ................................................................................................................ 28–39
HBI Channel Busy 1 Register ................................................................................................................ 28–40
HBI Channel Error 0 Register ............................................................................................................... 28–41
HBI Channel Error 1 Register ............................................................................................................... 28–42
HBI Channel Mask 0 Register ............................................................................................................... 28–43
HBI Channel Mask 1 Register ............................................................................................................... 28–44
HBI Control Register ............................................................................................................................ 28–45
Memory Interface Address Register ....................................................................................................... 28–46
Memory Interface Control Register ....................................................................................................... 28–47
Memory Interface Control Data 0 Register ........................................................................................... 28–48
Memory Interface Control Data 1 Register ........................................................................................... 28–49
Memory Interface Control Data 2 Register ........................................................................................... 28–50
Memory Interface Control Data 3 Register ........................................................................................... 28–51
Memory Interface Control Data Write Enable 0 Register ...................................................................... 28–52
Memory Interface Control Data Write Enable 1 Register ...................................................................... 28–53
Memory Interface Control Data Write Enable 2 Register ...................................................................... 28–54
Memory Interface Control Data Write Enable 3 Register ...................................................................... 28–55
Interrupt Enable Register ...................................................................................................................... 28–56
Channel Status 0 Register ...................................................................................................................... 28–59
Channel Status 1 Register ...................................................................................................................... 28–60
System Data Register ............................................................................................................................. 28–61
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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