Analog Devices ADSP-SC58 Series Hardware Reference Manual page 113

Peripheral ID1 Register ......................................................................................................................... 56–47
Peripheral ID2 Register ......................................................................................................................... 56–48
Peripheral ID3 Register ......................................................................................................................... 56–49
Peripheral ID4 Register ......................................................................................................................... 56–50
Status Register ....................................................................................................................................... 56–51
Synchronization Frequency Register ...................................................................................................... 56–52
TraceEnable Control Register ................................................................................................................ 56–53
TraceEnable Event Register .................................................................................................................... 56–54
CoreSight Trace ID Register .................................................................................................................. 56–57
Trigger Event Register ........................................................................................................................... 56–58
TraceEnable Start/Stop Control Register ............................................................................................... 56–61
ADSP-SC58x TAPC Register Descriptions ............................................................................................... 56–62
Debug Control Register ......................................................................................................................... 56–64
IDCODE Register ................................................................................................................................. 56–66
Secure Debug Key 0 Register ................................................................................................................. 56–67
Secure Debug Key 1 Register ................................................................................................................. 56–68
Secure Debug Key 2 Register ................................................................................................................. 56–69
Secure Debug Key 3 Register ................................................................................................................. 56–70
Secure Debug Key Control Register ....................................................................................................... 56–71
Secure Debug Key Status Register ......................................................................................................... 56–72
USERCODE Register ............................................................................................................................ 56–73
ADSP-SC58x Register List
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference cxiii