Analog Devices ADSP-SC58 Series Hardware Reference Manual page 46

Host Mode Reset................................................................................................................................. 27–42
Host Mode Suspend ............................................................................................................................ 27–43
Suspending and Resuming the Controller ........................................................................................... 27–43
Suspend or Resume by Inactivity on the USB Bus (L0 to L2 State) in Peripheral Mode................... 27–43
Suspend or Resume by Inactivity on the USB Bus (L0 To L2 State) in Host Mode.......................... 27–44
Suspend or Resume by an LPM Transaction (L0 To L1 State) in Peripheral Mode........................... 27–44
Suspend or Resume by an LPM Transaction (L0 to L1 State) in Host Mode.................................... 27–46
USB Event Control.................................................................................................................................... 27–47
Interrupt Signals .................................................................................................................................... 27–47
Interrupt Handling................................................................................................................................. 27–48
Reset Signals........................................................................................................................................... 27–49
Reset in Peripheral Mode .................................................................................................................... 27–49
USB Reset in Host Mode .................................................................................................................... 27–50
USB Programming Model ......................................................................................................................... 27–50
Peripheral Mode Flow Charts ................................................................................................................. 27–51
Host Mode Flow Charts ......................................................................................................................... 27–58
DMA Mode Flow Charts........................................................................................................................ 27–62
OTG Session Request ............................................................................................................................. 27–66
Starting a Session ................................................................................................................................ 27–66
Detecting Activity ............................................................................................................................... 27–67
Host Negotiation Protocol...................................................................................................................... 27–67
Data Transfer.......................................................................................................................................... 27–68
Loading or Unloading Packets from Endpoints ...................................................................................... 27–68
DMA Master Channels........................................................................................................................... 27–69
DMA Bus Cycles .................................................................................................................................... 27–70
Transferring Packets Using DMA ........................................................................................................... 27–71
Individual Rx Endpoint Packet............................................................................................................ 27–71
Individual Tx Endpoint Packet ........................................................................................................... 27–72
Multiple Rx Endpoint Packets............................................................................................................. 27–72
Multiple Tx Endpoint Packets............................................................................................................. 27–73
ADSP-SC58x USB Register Descriptions ................................................................................................. 27–74
xlvi ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference