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Bank 2 Control Register
The
register enables bank 2 accesses and configures the memory access features for this bank.
SMC_B2CTL
RDYABTEN (R/W)
ARDY Abort Enable
RDYPOL (R/W)
ARDY Polarity
RDYEN (R/W)
ARDY Enable
PGSZ (R/W)
Flash Page Size
Figure 11-19: SMC_B2CTL Register Diagram
Table 11-9: SMC_B2CTL Register Fields
Bit No.
(Access)
21:20
PGSZ
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
0
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
0
Bit Name
Flash Page Size.
The SMC_B2CTL.PGSZ bits select the flash page size, if page flash or sync burst
flash protocol has been enabled (SMC_B2CTL.MODE > 1). Note that the
SMC_B2CTL.PGSZ bits must be set to match the flash protocol of the external flash
memory device in the system. The typical SMC_B2CTL.PGSZ selection for external
devices supporting async flash or async flash page protocols is 4 or 8 words. The typi-
cal SMC_B2CTL.PGSZ selection for external devices supporting sync burst flash pro-
tocol is 16 words.
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
0 4 words
1 8 words
2 16 words
3 16 words
ADSP-SC58x SMC Register Descriptions
1
0
0
0
EN (R/W)
Bank 2 Enable
MODE (R/W)
Memory Access Mode
SELCTRL (R/W)
Select Control
17
16
0
0
11–33
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