Table of Contents
Advertisement
GIC Port 0 Enable ................................................................................................................................... 7–89
Software Generated Interrupt Priority Register ........................................................................................ 7–90
Shared Peripheral Interrupt Priority Register ........................................................................................... 7–91
Software Generated Interrupt Active Register .......................................................................................... 7–92
Software Generated Interrupt Control Register ....................................................................................... 7–93
Software Generated Interrupt Clear-Pending Register ............................................................................. 7–95
Software Generated Interrupt Pending Set Register ................................................................................. 7–96
Software Generated Interrupt Security Register ....................................................................................... 7–97
Shared Peripheral Interrupt Register ........................................................................................................ 7–98
Shared Peripheral Interrupt Active Register ............................................................................................. 7–99
Shared Peripheral Interrupt Configuration Register ............................................................................... 7–100
Shared Peripheral Interrupt Enable Clear Register ................................................................................. 7–101
Shared Peripheral Interrupt Enable Set Register .................................................................................... 7–102
Shared Peripheral Interrupt Pending Clear Register ............................................................................... 7–103
Shared Peripheral Interrupt Pending Set Register .................................................................................. 7–104
Shared Peripheral Interrupt Security Register ........................................................................................ 7–105
Shared Peripheral Interrupt Processor Targets Register .......................................................................... 7–106
Trigger Routing Unit (TRU)
TRU Features ................................................................................................................................................ 8–1
TRU Functional Description ......................................................................................................................... 8–1
ADSP-SC58x TRU Register List ................................................................................................................ 8–2
ADSP-SC58x TRU Interrupt List ............................................................................................................. 8–2
ADSP-SC58x Trigger List .......................................................................................................................... 8–3
TRU Definitions ...................................................................................................................................... 8–12
TRU Block Diagram ................................................................................................................................ 8–12
TRU Architectural Concepts ....................................................................................................................... 8–13
TRU Programming Model........................................................................................................................... 8–13
Programming Concepts ............................................................................................................................ 8–13
Programming Examples............................................................................................................................ 8–14
x
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Advertisement
Table of Contents
