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ADSP-SC58x UART Register Descriptions
Interrupt Mask Register
The
register indicates the interrupt mask status (unmasked, if set, or masked, if cleared) of the UART
UART_IMSK
status interrupt requests. This register is not a data register. Instead, it is controlled by the
UART_IMSK_CLR
register pair. Writing ones to the
quests, and writing ones to the
the enabled bits.
The
UART_IMSK
register is used to enable requests for system handling of empty or full states of UART data regis-
ters. Unless polling is used as a means of action, the UART_IMSK.ERBFI and UART_IMSK.ETBEI bits are nor-
mally set. Setting this register without enabling system DMA causes the UART to notify the processor of the data
inventory state using interrupts. For proper operation in this mode, system interrupts must be enabled, and appro-
priate interrupt handling routines must be present.
Each UART features three separate interrupt channels to handle the data transmit, data receive, and line status
events independently, regardless of whether DMA is enabled or not. If no DMA channels are assigned to the UART,
set the UART_IMSK.ELSI bit to reroute the transmit and receive interrupts to the status interrupt request output.
With system DMA enabled, the UART uses DMA to transfer data to or from the processor. Dedicated DMA chan-
nels are available for receive and transmit operations. Line error handling can be configured independently from the
receive or transmit setup.
The DMA of the UART is enabled by first setting up the system DMA control registers and then enabling the
UART_IMSK.ERBFI and UART_IMSK.ETBEI interrupts. This configuration is because the interrupt request
lines double as DMA request lines. Depending on whether DMA is enabled or not, upon receiving these requests,
the DMA control unit either generates a direct memory access or passes the UART interrupt on to the system inter-
rupt handling unit(s). However, the error interrupt for the UART goes directly to the system interrupt handling
unit(s), bypassing the DMA unit completely.
17–32
UART_IMSK_SET
register disables (masks) them. Reads from either register return
UART_IMSK_CLR
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
UART_IMSK_SET
register enables (unmasks) interrupt re-
and
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