Analog Devices ADSP-SC58 Series Hardware Reference Manual page 173

ADSP-SC58x CGU Register Descriptions
Table 3-13: CGU_DIV Register Fields (Continued)
Bit No.
(Access)
29 ALGN
(R0/W)
28:22 OSEL
(R/W)
20:16 DSEL
(R/W)
15:13 S1SEL
(R/W)
12:8 SYSSEL
(R/W)
3–22
Bit Name
Align.
The CGU_DIV.ALGN directs the CGU to align the PLL-based clocks. The divisor se-
lections (CGU_DIV.CSEL, CGU_DIV.SYSSEL, CGU_DIV.S0SEL,
CGU_DIV.S1SEL, CGU_DIV.DSEL, and/or CGU_DIV.OSEL) do not have to
change.
OCLK Divisor.
The CGU_DIV.OSEL selects the divisor in the OCLK equation:
OCLK frequency = (SYS_CLKIN frequency / (DF+1)) * MSEL / CGU_DIV.OSEL
Where the value of CGU_DIV.OSEL is between 1 and 127.
DCLK Divisor.
The CGU_DIV.DSEL selects the divisor in the DCLK equation:
DCLK frequency = (SYS_CLKIN frequency/(DF+1)) MSEL/CGU_DIV.DSEL
Where the value of CGU_DIV.DSEL is between 1 and 31.
SCLK 1 Divisor.
The CGU_DIV.S1SEL selects the divisor in the SCLK1 equation:
SCLK1 frequency = (SYSCLK frequency) / CGU_DIV.S1SEL
Where the value of CGU_DIV.S1SEL is between 1 and 7.
SYSCLK Divisor.
The CGU_DIV.SYSSEL selects the divisor in the SYSCLK equation:
SYSCLK frequency = (SYS_CLKIN frequency/(DF+1)) MSEL/CGU_DIV.SYSSEL
Where the value of CGU_DIV.SYSSEL is between 1 and 31.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 No Action
1 Align PLL Clocks
0 OSEL = 128
1-127 OSEL = 1 to 127
0 DSEL = 32
1-31 DSEL = 1 to 31
0 S1SEL = 8
1-7 S1SEL = 1 to 7
0 SYSSEL = 32
1-31 SYSSEL = 1 to 31