Analog Devices ADSP-SC58 Series Hardware Reference Manual page 259

SEC Block Diagram
SEC Fault Interface (SFI)
FCTL
FSTAT FSID
SSI
TO (Trigger Out)
SR (System Reset)
Event Actions FDELAYCUR FDELAY
(Fault / COP)
Figure 7-3: SFI Block Diagram
Fault Management
System sources can be enabled as fault sources in the SEC_SCTL[n] register. When a source enabled as a fault
moves to pending, it is forwarded to the SFI as a fault indication. The pending bit (SEC_FSTAT.PND) indicates a
source has signaled a fault assertion but it has not yet triggered the event actions (if delay is enabled). The SEC fault
interface sets the SEC_FSTAT.PND bit when the fault source ID register (SEC_FSID) is updated on assertion of
a fault source input. The system source pending triggers a fault pending and after a programmable delay the fault
moves to active. Event actions then execute if appropriate action is not taken by the core. The SEC_FSTAT.ACT
bit indicates that the SEC has received a fault source input, the delay has expired, and the fault actions are enabled.
The SEC_FSTAT.NPND bit indicates if one or more sources have signaled a fault assertion, but the input has not
yet triggered the fault pending detection in the SEC fault interface. The SEC sets the SEC_FSTAT.NPND bit
when the fault interface detects assertion of any enabled fault source input, while either the SEC_FSTAT.PND or
SEC_FSTAT.ACT bits are set. The SEC clears the SEC_FSTAT.NPND bit when there are no fault sources wait-
ing.
A fault indication from an external device can also be detected on sampling the fault signals. When a fault is detec-
ted the SEC_FSTAT.ACT and SEC_FSID.FEXT bits are set. The assertion of either signal results in a fault in-
put detection.
The SEC_FEND register receives a fault end indication from the core. The core writes the SID of the fault to the
SEC_FEND register. If the SID matches the value in the SEC_FSID register, the SEC_FSTAT.PND and
SEC_FSTAT.ACT bits are cleared.
More information can be found in the Fault Management Interface Programming Model section.
SEC Core Interface (SCI)
The SCI manages communication between the corresponding core and the SEC. The SEC prioritizer (SPR) of the
SCI receives pending, active, and priority information from the SSI for each system event source assigned to this
SCI. The SPR determines the highest-priority pending system event and the SCI determines whether it propagates
7–14 ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference