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Programming Model
called a self-restart trip condition. If the trip condition is not active at the next period boundary of the
PWMTMRy that the channel is using, the status register bit is cleared. The outputs are restored.
The trip input pins have an external pull-down resistor on the chip pin. If the pin becomes disconnected, the pro-
cessor disables the PWM.
In addition to the hardware trip conditions, a global software trip bit in the
forced fault trip condition. When the global software trip bit is set to 1, irrespective of the values in the
register, it sets all the PWM_STAT.FLTTRIPA bits and also gates the channel outputs. To remove
PWM_TRIPCFG
the trip condition from the channel, perform a W1C on the PWM_STAT.FLTTRIPA bit of the particular channel.
If the PWM_TRIPCFG.EN0A bit is set to 1 to, for any channel, then the occurrence of a fault condition on the
PWMTRIPy bit is logged in the PWM_STAT.FLTTRIPA register bit. If the corresponding PWM_IMSK.TRIP0
bit = 1, then an interrupt request is generated. Tripping a channel output does not interfere with PWM_SYNC gener-
ation.
The Operation Under Hardware Fault Conditions figure shows an example where PWMTRIP0 is enabled on chan-
nel A as self-restart trip. Channel A works with the PWM_CHANCFG.POLAH bit =1. In period 2, the PWM_AH
signal is full on modulated, and tries to rise at the period boundary where the self-restart occurs for the channel.
However, since the low-side output of the channel was only recently removed due to a trip, the rise edge on
PWM_AH is delayed until the emergency dead-time period is over. PWMTRIP1 is enabled on channel B as a fault
trip. Channel B works with the PWM_CHANCFG.POLAH bit =0. PWMTRIP1 stays low for an extended time peri-
od. The first processor write to reenable the channel output fails. The second processor write passes since the fault
condition has gone away.
Dead time is ensured on re-enabling the channel outputs after trip.
NOTE:
Programs must not allow changes in the configuration or enable bits of
NOTE:
10 clock cycles of when the external trip pulse toggles. (The configuration or enable bits of
PWM_TRIPCFG
unexpected behavior occurs.
Programming Model
The following sections provide general (and some application-specific) programming steps for configuring and using
the PWM module.
•
Programming Model for Three-Phase AC Motor Control
Programming Model for Three-Phase AC Motor Control
The PWM Module and Interaction with System figure shows how the PWM unit (green) interfaces to both software
(blue) and hardware (yellow). The software configures the unit, calculates duty cycles (Duty A, Duty B, Duty C),
and services the interrupts generated by the module (PWM SYNC IRQ, TRIP IRQ). The hardware applies the gate
signals (AH, AL, BH, BL, CH, CL) to the inverter and provides an over-current trip signal back to the unit
(TRIP0).
19–34
register select between trip enable and disable). If this time frame is not followed, then
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
PWM_CTL
register allows for a software-
register within ±
PWM_TRIPCFG
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