Global Control Registers; Adv7604 Revision Identification; Power Modes; Power-Down Modes - Analog Devices Advantiv ADV7604 Hardware Manual

3 Global Control Registers

The register control bits described in this section affect the whole chip and are not dependent on the
analog digitizer mode or HDMI receiver mode for which the ADV7604 is configured.
3.1

ADV7604 Revision Identification

The revision can be read back via RD_INFO[7:0].
RD_INFO[7:0], IO Map, Address 0x11, [7:0]
Function
IDENT[7:0]
00000001
00000010
00000011
3.2

Power Modes

3.2.1

Power-down Modes

The ADV7604 supports the following power-down modes:
• Power-down mode 0
• Power-down mode 1
3.2.1.1 Power-down Mode 0
In power-down mode 0, selected sections and pads are kept active to provide EDID and +5 V anti
glitch filter functionality.
In power-down mode 0, all the sections of the part are disabled except for the following blocks:
2
• I
C slave section
• EDID/Repeater controller
• EDID ring oscillator
The ring oscillator provides a clock to the EDID/Repeater controller (refer to Section 7.2) and
the +5 V power supply anti glitch filter (refer to Section 7.1). The clock output from the ring
oscillator runs approximately at 50 MHz.
The following are the only pads enabled in power-down mode 0:
2
• I
C pads SCL and SDA
• +5 V pads:
RXA_5V
RXB_5V
Rev. F August 2010
Description
ES1 revision
ES2 revision
Final revision
28
ADV7604