Table of Contents
Advertisement
Operating Modes
Since many of the functions needed by the debug monitor and the ICE
overlap, most of the debug functions in the TigerSHARC processor are
shared between the two methods. There are some features that need to be
optionally restricted by the ICE so that the debugger can be used in super-
visor mode.
Debug capabilities are available either through the ICE or through the
supervisor mode. As already mentioned, the ICE mode is accessed through
the JTAG port. The supervisor mode is entered via
a specific software watchpoint. When the TigerSHARC processor is in
supervisor or emulation mode, it has complete access to all of the Tiger-
SHARC processor's resources.
Table 9-1 details debug concepts and capabilities.
Operating Modes
The TigerSHARC processor operates in one of three modes—emulator,
supervisor, and user. In user and supervisor modes, all instructions are
executed normally. In user mode, however, the register access is limited.
In emulation mode, none of the control flow instructions (excluding
True, RTI (np);
problems and it is illegal to use them in emulation. Operating modes are
discussed in "Operation Modes" on page 3-2.
Debug Resources
Special Instructions
The TigerSHARC processor supports special instructions (traps) which
are used to aid system debugging. These instructions are required to
implement both software breakpoints (in debuggers) and operating system
calls (for OS kernels).
9-2
) may be used—control flow instructions may cause
Reset
ADSP-TS101 TigerSHARC Processor
Hardware Reference
, an exception, or
If
Advertisement
Table of Contents
